| Problem with make [message #146867] |
Wed, 15 June 2005 13:20 |
Eclipse User |
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Originally posted by: jonkersbart.gmail.com
Hey,
I have a little problem with a make file that I want to use with
different compilers en options.
This is the makefile:
CC = gcc
CFLAGS = -Wall -O3
LDFLAGS =
all: clean configurationunit
configurationunit: configurator.o
$(CC) $(LDFLAGS) $(CFLAGS) -o configurationunit configurator.o
configurator.o: configurator.c configurator.h slideshow.h
$(CC) $(CFLAGS) -c configurator.c
clean:
rm -f *.o *.bb *.bbg *.gcov *.out configurationunit
Now I create different Make Targets for the project, where I change the
Build command from make to make CC=<compiler> CFLAGS=<options>
LDFLAGS=<options>. (example: make CC=arm-linux-gcc CFLAGS=-Wall)
When an option is one parameter there is no problem, but when I want to
give multiple CFLAGS it doesn't work.
I have tried the following things but not one of them works:
make CC=arm-linux-gcc CFLAGS=-Wall -g
make CC=arm-linux-gcc CFLAGS="-Wall -g"
make CC=arm-linux-gcc "CFLAGS=-Wall -g"
When I type make CC=arm-linux-gcc CFLAGS="-Wall -g" in a shell, it works.
Has somebody a solution for this problem or is there a better way to
manage multiple compilers and options in a single make file.
I know that you can add multiple targets in your make file, but that is
a lot of typing work.
I use eclipse 3.0.2 an CDT 2.1.1.
Thanks a lot,
Bart
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